Conventionally, a metal oxide semiconductor field effect transistor (MOSFET) is known as a semiconductor device having a switching function (see, for example, Patent Document 1). The Patent Document 1 discloses a trench gate MOSFET (semiconductor device) in which a gate electrode is embedded in a trench formed in a semiconductor layer.
FIG. 31 is a cross sectional view illustrating a structure of a conventional MOSFET (semiconductor device) disclosed in the Patent Document 1. With reference to FIG. 31, the conventional MOSFET includes an N+ type semiconductor substrate 501 and an epitaxial layer 502 formed on the upper surface of the semiconductor substrate 501. This epitaxial layer 502 includes an N− type impurity region (drain region) 502a, a P type impurity region 502b and an N+ type impurity region (source region) 502c formed in this order from the semiconductor substrate 501 side. In addition, the N+ type impurity region 502c is formed in a predetermined region on the P type impurity region 502b, so that both the P type impurity region 502b and the N+ type impurity region 502c contact with the source electrode 507 that will be described later.
In addition, in the epitaxial layer 502, there is formed a trench 503 that penetrates the N+ type impurity region 502c and the P type impurity region 502b so as to reach a halfway depth of the N− type impurity region 502a. A gate electrode 505 is formed inside the trench 503 via the gate insulator film 504. In addition, in a predetermined region on the upper surface of the epitaxial layer 502, there is formed an interlayer insulator film 506 that closes an opening of the trench 503.
In addition, on the upper surface of the epitaxial layer 502, there is formed a source electrode 507 so as to cover the interlayer insulator film 506. In addition, a drain electrode 508 is formed on the back surface of the semiconductor substrate 501.
In the conventional MOSFET having the structure described above, the applied voltage to the gate electrode 505 is changed for controlling on and off.
Specifically, when a predetermined positive potential is applied to the gate electrode 505, minority carrier (electrons) in the P type impurity region 502b is attracted to the trench 503 side, so there is formed an inversion layer 509 that connects the N− type impurity region (drain region) 502a with the N+ type impurity region (source region) 502c. Thus, current can flow between the source electrode 507 and the drain electrode 508 via the inversion layer 509. As a result, the MOSFET is turned on. In other words, the conventional MOSFET makes the inversion layer 509 function as a channel, which is formed to connect the N− type impurity region (drain region) 502a with the N+ type impurity region (source region) 502c. 
In contrast, when the application of the predetermined positive potential to the gate electrode 505 is stopped, the inversion layer (channel) 509 is deleted so that the current flowing between the source electrode 507 and the drain electrode 508 can be interrupted. As a result, the MOSFET is turned off.
Patent Document 1: JP-A-2001-7149